Application specific integrated circuit (ASIC) design methodologies allow for certain components such as memory to be specified and included in specific circuit designs using macros. However, conventional memory macros typically found in existing structured ASIC designs embed a substantial amount of logic to support all the memory features (e.g. redundancy, ECC and etc.) that may potentially be desired by all users. If certain designs do not actually need to include a memory having all of these features, using these macros requires a larger silicon area than is actually necessary to build the memory. Moreover, using these macros might lead to a reduction in memory performance if the extra/unused features are built on a critical path in the memory. Still further, extra parasitic capacitance contributed by these extra functions/logic will result in higher memory power consumption than is otherwise necessary.
U.S. Pat. Nos. 9,336,342, 9,218,872, 9,075,930, 9,019,782, 8,837,249 and 8,631,365 describe various aspects of conventional memory macros but they all suffer from the problems described above, among others.
Accordingly, a need exists for a solution to these and other problems.